1. Field of the Invention:
The present invention relates generally to integrated circuit memories, and more specifically to memory cells for dynamic random access memory devices.
2. Description of the Prior Art:
Dynamic random access memory (DRAMs) are widely used in the electronic industry. DRAM memory cells typically use a field effect transistor as a pass gate, and a capacitor as a storage node. The current state of the DRAM cell is represented by the presence or absence of charge on the storage node. The quality of a DRAM cell is strongly effected by the size of the capacitor. A smaller capacitance for the storage node results in lower signal-to-noise ratios since a smaller charge can be stored on the capacitor. Smaller capacitors also require shorter refresh times for the DRAM cells.
As memory capacities increase, the density of memory cells on an integrated circuit increases and each cell must be made smaller. As cell sizes shrink, problems with small capacitors become more difficult to deal with during cell design. Efforts have been made to improve the capacitance of the storage node by increasing the capacitor plate surface area using a number of techniques. These include the placement of transistors in relatively deep trenches, or pits, excavated from the substrate, and placing capacitors on the sides of vertical pillars. The processing technologies used to fabricated such structures are relatively difficult to control, resulting in a large variability in device properties. In addition, they tend to increase the complexity of the process flow, adding to device cost.
It would be desirable to provide a capacitor suitable for DRAM cells which has an increased capacitance. It would be further desirable to provide such a capacitor which does not greatly increase the overall cell size and which does not add greatly to the complexity of integrated circuit processing.